1. Field of the Invention
The present invention relates to a semiconductor memory device for generating a startup timing of an internal circuit by using a dummy circuit. In particular, the present invention relates to a semiconductor memory device capable of relieving a dummy circuit without increasing a chip area to enhance a yield, thereby optimizing a startup timing of an internal circuit.
2. Description of the Related Art
Various methods have been considered for generating a startup signal of an amplifier for amplifying data read from a memory cell by using a dummy memory cell, and allowing the startup timing of the amplifier to precisely follow the variation in read timing of the memory cell caused by a process, a voltage, and the like in a conventional semiconductor memory device.
FIGS. 25 to 28 schematically show circuit configurations disclosed in “IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, November 2001, pp. 1738-1744” and U.S. Pat. No. 6,212,117, as exemplary configurations of conventional semiconductor memory devices.
In FIG. 25, reference numeral 500 denotes a memory array, 501 and 502 denote dummy columns included in the memory array 500, and 504 denotes a plurality of normal columns included in the memory array 500, respectively. Herein, the normal columns refer to those columns other than the dummy columns.
Furthermore, reference numeral 505 denotes a dummy control circuit connected to a memory array 500, 507 denotes an amplifier control circuit that receives an output from the dummy columns 502, 508 denotes a column selector connected to the normal columns 504, 509 denotes an amplifier connected to the column selector 508 and the amplifier control circuit 507, and 510 denotes a row decoder connected to the memory array 500, respectively.
FIG. 26 shows a partial configuration of the memory array 500 shown in FIG. 25. In FIG. 26, reference numeral 511 denotes normal memory cells, and SRAMs are used often as the normal memory cells. Reference numeral 512 denotes dummy cells included in the dummy column 501, and 513 denotes dummy cells included in the dummy column 502, respectively.
FIG. 27 shows a configuration of the memory cell 511 shown in FIG. 26. FIG. 28 shows internal configurations of the dummy cells 512 and 513 shown in FIG. 26 and an interconnection configuration therebetween.
As shown in FIG. 28, transistors constituting the dummy cells 512 and 513 have the same size as that of a transistor constituting the memory cell 511 shown in FIG. 27. Latch circuits included in the dummy cells 512 and 513 are fixed at a predetermined level.
As shown in FIG. 26, the memory cell 511 is connected to word lines WL0 to WLx connected to the row decoder 510 in a row direction, and is connected to common bit lines BL and NBL in a column direction.
As shown in FIG. 26, n dummy cells 512 among the plurality of dummy cells 512 are connected to a dummy word line DWL on an output side of the dummy control circuit 505, and the other dummy cells 512 are connected to a ground line. n dummy cells 512 are arranged successively from a position close to the amplifier 509.
Among the plurality of dummy cells 513, n dummy cells 513 are connected to a dummy word line DWL on an output side of the dummy control circuit 505, and the other dummy cells 513 are connected to a ground line. Furthermore, the plurality of dummy cells 513 are connected to a common dummy bit line DBL, and the dummy bit line DBL is connected to the amplifier control circuit 507. n dummy cells 513 also are arranged successively from a position close to the amplifier 509.
When a conventional semiconductor memory device configured as described above is operated, any of the word lines WL0 to WLx connected to the row decoder 510 is selected, and the data in the memory cell 511 connected to the selected word line is read to the bit lines BL and NBL.
The bit lines BL, NBL, and the dummy bit line DBL are previously precharged to a high level, and are in a floating state when the word lines WL0 to WLx are selected. Furthermore, since a plurality of normal columns 504 are present, the data in the plurality of memory cells 511 connected to the selected word line is read to the bit lines BL and NBL. In this case, the data in the particular bit lines BL and NBL is selected by the column selector 508.
At almost the same timing as the timing at which the word lines WL0 to WLx are selected, the dummy word line DWL on an output side of the dummy control circuit 505 is driven, and the transistors constituting the n dummy cells 513 allow the dummy bit line DBL to change from a high level to a low level at a slew rate that is n times that of the memory cell 511.
Then, a signal level of the dummy bit line DBL is detected, whereby the amplifier control circuit 507 generates an amplifier startup signal SAE. The amplifier 509 amplifies the data in the selected particular bit lines BL and BNL at a timing at which the amplifier startup signal SAE is input.
For example, in the case where the amplifier 509 is desired to be started up when a supply voltage is 1.2 V, and the potential difference between the read data (BL) and the read data (NBL) from the memory cell 511 is 100 mV, if the number of the dummy cells 513 to be selected is set to be ‘6’, the dummy bit line DBL changes to 600 mV (i.e., a potential that is a half of a supply voltage) at a desired amplifier startup timing. Thus, the amplifier startup signal SAE can be generated merely by using a simple CMOS gate without using a complicated potential detection circuit.
However, in the above-mentioned conventional semiconductor memory device, although wiring loads of the bit lines BL and NBL connected to the memory cell 511 are included in the dummy circuit, a load of the column selector 508 connected to the bit line is not included in the dummy circuit. Thus, the generation of a SAE signal based on a dummy bit line signal is delayed from the desired amplifier startup timing.
Furthermore, in the above-mentioned conventional semiconductor memory device, the dummy cell 512 for driving the dummy bit line DBL is placed at a position close to the amplifier 509 with respect to the memory array 500. In the case where the memory cell 511 placed in an end portion on an opposite side of the amplifier 509 is selected, the delay due to the wiring resistance of the bit lines BL and NBL is not reflected. Therefore, the generation of a SAE signal based on a dummy bit line signal is advanced from the desired amplifier startup timing.
Furthermore, in the above-mentioned conventional semiconductor memory device, the dummy cell 512 is operated at every read access to the memory array 500. In the case where there is a defect in the dummy cell 512 itself, the amplifier cannot be started up at the desired timing or the amplifier cannot be started up, resulting a defective product.